Part Number: ADS8363
I’m trying to use the ADS8363 with its advertised 1MHz sampling rate and have some problems with the behavior of the BUSY signal. I’m using the full clock mode 1 with a 40MHz clock and channel information disabled (CID=1). I have RD and CONVST connected together so I can’t control them individually.
The datasheet states (table 7.9 switch characteristics, t_D2) that the BUSY signal should transition to low after the 24th rising edge in full clock mode. However the timing diagram in figure 2 seems to show the 25th rising edge. Actually I’m seeing both variants in my setup and I can switch between them by inserting additional clock cycles. Normally I output 40 clock cycles per conversion, but using 41 cycles for one conversion switches between BUSY going low on the 24th or 25th rising edge.
So normally I would assume the worst case and then start reading on the 25th cycle, but then the LSB of the data overlaps with the next conversion. When setting CONVST/RD high the ADC seems to drive SDOx low and my LSB is always 0. Similarly starting to read on the 24th cycle gives a corrupt MSB in the case when BUSY goes low at the 25th rising edge.
How do I use the ADS8363 in full clock mode with 1MHz sampling rate? I’ve attached some screenshots showing the timing of CONVST/RD. The signals are as follows: CH1 -> CLK, CH2 -> CONVST/RD, CH3 -> BUSY.
CONVST rising edge:
CONVST falling edge:
