ADS54J54EVM: Question about JESD204B data lanes length match

Part Number: ADS54J54EVM

Hi,

In the schematics of  ADS54J54EVM  page 4 it ca be read: 

"HIGH SPEED DIFF PAIRS
DA*, DB*, DC* & DD*
DO NOT HAVE TO MATCH EACH OTHER IN LENGTH
THE P & N ON EACH PAIR MUST MATCH IN LENGTH"

But when I look at the PCB tracks for these signal they are in fact matched in length with each other as can be seen below. I am doing a board with exactly the same configuration that is trying to connect to a FPGA through FMC connector, how should I do?

Regards/Ramin