Hello
I am implementing an PCM3168A Audio Codec into the BeagleBoard by using the ALSA framework. And so far i got my first audio signals out of the PCM3168 :-)
Till now i use the hardware control pins to setup the codec but i want to change that by using I2C for that purpose. For the clk signal generation an PLL1707 is used.
What i do not understand properly is whether the PCM3168 uses the SCKI system clock just as an reference when using the codec in master mode (internal PLL ?) and MSDA[2:0] DAC Master/slave mode select registers (and MSAD[2:0]) do configure the correct LRCKAD/DA and BCKAD/DA or whether i have to adjust also the external clock (applied to SCKI) to the appropriate mode.
And the second question i have is how i can calculate the delay which occurs between applying the digital audio sample and the converted analog audio signal (for the DAC and vice versa for the ADC). Is it just the formula from the digital filter group delay -> DAC(single, dual) 28/fs or is there an additional delay to consider.
Thanks
Wendelin