Compiler/TMS320C6748: C6748 Custom Memory Map

Part Number: TMS320C6748

Tool/software: TI C/C++ Compiler

Hi,

I have a TMS320C6748 custom board with a 256 DDR.

I made a custom memory map and currently having a problem with booting. But, it works well in simulation mode. Only troubles with flash boot. flash boot doesn't work.

I have applied some extreme values for testing purpose. mem size will be reduced in the real session. This is due to compiling USB driver.

[at the end of .cfg file]

Program.sectMap[".bss:extMemCache:ramdisk"]                 = new Program.SectionSpec();
Program.sectMap[".bss:extMemCache:ramdisk"].loadSegment     = "APP_CACHED_BIOS_RSVD_MEM";
Program.sectMap[".bss:extMemCache:ramdisk"].type            = "NOLOAD"

[local .cmd file]

-heap 0x80000
-stack 0x80000

MEMORY
{
      FLASH_CS2     org=0x60000000 len=0x02000000 /* AEMIF CS2 region */
      FLASH_BOOT    org=0x62000000 len=0x02000000 /* AEMIF CS3 region */
      FLASH_CS4     org=0x64000000 len=0x02000000 /* AEMIF CS4 region */
}

SECTIONS
{

    .aemif_mem :
    {   
    } > FLASH_BOOT, RUN_START(NANDStart)

    "CFG" > DDR_CFG

    "DDR" > DDR

    .ddrram  :
    {   
        . += 0x04000000;
    } > APP_CODE_MEM, type=DSECT, RUN_START(EXTERNAL_RAM_START), RUN_END(EXTERNAL_RAM_END)
}

[ custom Platform.xdt]

metaonly module Platform inherits xdc.platform.IPlatform {

/*config int DDR_SIZE = 0x07FF33EC;*/

config int KB = 1024;
config int MB = KB*KB;

config int SBL_SIZE = 4*KB;

config int DDR_ADDR = 0xC0000000;
config int DDR_SIZE = 10*MB;

config int APP_CODE_MEM_ADDR = DDR_ADDR+DDR_SIZE+SBL_SIZE;
config int APP_CODE_MEM_SIZE = 30*MB;

config int APP_CACHED_DATA_MEM_ADDR = APP_CODE_MEM_ADDR+APP_CODE_MEM_SIZE;
config int APP_CACHED_DATA_MEM_SIZE = 30*MB;

config int APP_UNCACHED_DATA_BLK3_MEM_ADDR = APP_CACHED_DATA_MEM_ADDR+APP_CACHED_DATA_MEM_SIZE;
config int APP_UNCACHED_DATA_BLK3_MEM_SIZE = 30*MB;

config int APP_CACHED_DATA_BLK1_MEM_ADDR = APP_UNCACHED_DATA_BLK3_MEM_ADDR+APP_UNCACHED_DATA_BLK3_MEM_SIZE;
config int APP_CACHED_DATA_BLK1_MEM_SIZE = 30*MB;

config int APP_CACHED_DATA_BLK2_MEM_ADDR = APP_CACHED_DATA_BLK1_MEM_ADDR+APP_CACHED_DATA_BLK1_MEM_SIZE;
config int APP_CACHED_DATA_BLK2_MEM_SIZE = 30*MB;

config int APP_CACHED_BIOS_RSVD_MEM_ADDR = APP_CACHED_DATA_BLK2_MEM_ADDR+APP_CACHED_DATA_BLK2_MEM_SIZE;
config int APP_CACHED_BIOS_RSVD_MEM_SIZE = 30*MB;

config int DDR_CFG_ADDR = APP_CACHED_BIOS_RSVD_MEM_ADDR+APP_CACHED_BIOS_RSVD_MEM_SIZE;
config int DDR_CFG_SIZE = 10*MB;

    config ti.platforms.generic.Platform.Instance CPU =
        ti.platforms.generic.Platform.create("CPU", {
            clockRate:      300.0,    
            catalogName:    "ti.catalog.c6000",
            deviceName:     "TMS320C6748",
            customMemoryMap:
           [    
                ["IRAM",                        {name: "IRAM",                      base: 0x11800000,   len: 0x00040000,   space: "code/data",     access: "RWX",}],
                ["IROM",                        {name: "IROM",                      base: 0x11700000,   len: 0x00100000,   space: "code/data",     access: "RX", }],
                ["L3_CBA_RAM",                  {name: "L3_CBA_RAM",                base: 0x80000000,   len: 0x00020000,   space: "code/data",     access: "RWX",}],
                ["DDR",                         {name: "DDR",                       base: DDR_ADDR,     len: DDR_SIZE,   space: "code/data",     access: "RWX",}],
                ["APP_CODE_MEM",                {name: "APP_CODE_MEM",              base: APP_CODE_MEM_ADDR,   len: APP_CODE_MEM_SIZE,   space: "code/data"}],
                ["APP_CACHED_DATA_MEM",         {name: "APP_CACHED_DATA_MEM",       base: APP_CACHED_DATA_MEM_ADDR,   len: APP_CACHED_DATA_MEM_SIZE,   space: "code/data",}],
                ["APP_UNCACHED_DATA_BLK3_MEM",  {name: "APP_UNCACHED_DATA_BLK3_MEM",base: APP_UNCACHED_DATA_BLK3_MEM_ADDR,   len: APP_UNCACHED_DATA_BLK3_MEM_SIZE,   space: "code/data",}],
                ["APP_CACHED_DATA_BLK1_MEM",    {name: "APP_CACHED_DATA_BLK1_MEM",  base: APP_CACHED_DATA_BLK1_MEM_ADDR,    len: APP_CACHED_DATA_BLK1_MEM_SIZE,   space: "code/data",}],
                ["APP_CACHED_DATA_BLK2_MEM",    {name: "APP_CACHED_DATA_BLK2_MEM",  base: APP_CACHED_DATA_BLK2_MEM_ADDR,   len: APP_CACHED_DATA_BLK2_MEM_SIZE,   space: "code/data",}],
                ["APP_CACHED_BIOS_RSVD_MEM",    {name: "APP_CACHED_BIOS_RSVD_MEM",  base: APP_CACHED_BIOS_RSVD_MEM_ADDR,    len: APP_CACHED_BIOS_RSVD_MEM_SIZE,   space: "code/data",}],
                ["DDR_CFG",                     {name: "DDR_CFG",                   base: DDR_CFG_ADDR,   len: DDR_CFG_SIZE,   space: "code/data",     access: "RWX",}],
           ],

          l2Mode: "0k",
          l1PMode: "32k",
          l1DMode: "32k",
    });
    
instance :
    
    override config string codeMemory  = "APP_CODE_MEM";   
    override config string dataMemory  = "APP_CODE_MEM";    
    override config string stackMemory = "IRAM";

    config String l2Mode = "0k";
    config String l1PMode = "32k";
    config String l1DMode = "32k";
}

What am I doing wrong here?