TMS320F28377S: EPWM w/deadband, one clock glitch at the beginning of Falling Edge Delay

Part Number: TMS320F28377S

I believe this is some kind of chip's idiosyncrasity that I have tried to fix programmatically but was not able so far.

I am using EPWM (no HRPWM) with deadband, using ePWMxA as input to both RED and FED (twice as long as RED) and active high outputs.

When OutA falls, there is always a one clock low pulse (exactly 200nS) on OutB and then FED continues normally.

Please see picture. OutA is on top, OutB on bottom.

I tried to use separate A/B inputs, inverted inputs and outputs and anytime the output is active high, the pulse was there.

When OutB is set to active low, the pulse is not there probably because it is also low.

Any ideas what it is and how to get rid of it?

Martin