DRA750: DRA75 QSPI read timing query

Part Number: DRA750

Hi,

We are using "DRA752BPGABCQ1" in our circuit and validating QSPI read timings. Can you please clarify read timing of the processor. 

As per TRM (referring to table, page#), the processor clock reads the slave device data on every falling edge of the clock. Please refer to below datasheet timing expert.

The slave device (serial memory) send the data on falling edge and if processor also reads data on falling edge, the setup/holdtime can not be met. We captured actual circuit waveform and shared below.

Can you please clarify whether the processor reads the data on falling edge or rising edge of the clock?

thank you