ADC3444: is it necessary lvda adc DCLK_p/n to a fpga dedicated clock input pins like MRCC of xilinx 7 serials???

Please help me with this question: 

I got a customized board using an lvds ADC adc3444 and Xilinx 7 serial. I found the  DCLK_p/n and FCLK_p/n are not connected to MRCC or SRCC, instead, to common lvds pairs. 

1) Isn't it necessary lvda adc DCLK_p/n to a clock dedicated pairs, such as MRCC or SRCC??? 

PS: My previous understanding is that 'Connect the bit clock DCLK_p/n to an MRCC differential clock input. I did read a doc saying: 

" For an ADC with serial LVDS output implementation, half of an IO-bank can handle all connections from
the ADC:
• Connect the bit clock DCLK_p/n to an MRCC differential clock input.
• Connect the frame clock FCLK_p/n to the neighbor SRCC differential clock input.

"