Part Number: AWR1243
I'm not able to configure the device in SDR mode. It always operates in DDR mode.
First I identified the following three structure variables to change the data rate and mode:
typedef struct rlDevDataPathClkCfg
{
#ifndef MMWL_BIG_ENDIAN
/**
* @brief Clock COnfiguration \n
0 -SDR Clock \n
1 - DDR Clock (Only valid value for CSI2) \n
*/
rlUInt8_t laneClkCfg;
/**
* @brief Data rate selection \n
0000b - 900 Mbps (DDR only) \n
0001b - 600 Mbps (DDR only) \n
0010b - 450 Mbps (SDR, DDR) \n
0011b - 400 Mbps (DDR only) \n
0100b - 300 Mbps (SDR, DDR) \n
0101b - 225 Mbps (DDR only) \n
0110b - 150 Mbps (SDR, DDR) \n
Others - Reserved \n
*/
rlUInt8_t dataRate;
typedef struct rlDevHsiClk
{
/**
* @brief High Speed Interface Clock configurations. Below table indicates possible values
for different data rate supported \n
HSICLKRATECODE (corresponding datarate in Mbps): \n
SDR - 0x5(900 mbps), 0xA(600 mbps), 0x6(450 mbps), 0x2(400 mbps),
0xB(300 mbps), 0x7(225 mbps) \n
DDR - 0xD(900 mbps), 0x9(600 mbps), 0x5(450 mbps), 0x1(400 mbps),
0xA(300 mbps), 0x6(225 mbps ), 0xB(150 mbps) \n
*/
rlUInt16_t hsiClk;
/**
* @brief Reserved for future use
*/
rlUInt16_t reserved;
}rlDevHsiClk_t;
First, why are there two parameters to set the data rate? This makes no sense?
Second, when I change laneClkCfg parameter from 1 to 0 it has no effect on the clock. The clock is still operating in DDR mode?
When I set laneClk=0, dataRate=8, and hsiClk=10, I get a 150MHz clock and the data also toggles at 150MHz? The clock should toggle twice the data rate not the same for SDR?
Daniel