Part Number:TMS570LS3137
Hi Team,
This is the continuation of https://e2e.ti.com/support/microcontrollers/hercules/f/312/t/810075.
Could see that channel 10 and 12 in ESM group 2 will trigger for address parity errors in RAM and corresponding test case in sys_selftest.c file is in checkRAMAddrParity.
Please help in answering below:
1. We executed this method to reproduce the problem of address parity error and in the above mentioned method, once the error is reproduced (by checking the RAMERRSTATUS register), the method
tries to clear the bits 6 and 8 of esm group 2 status register. Please see below snapshot.
esmREG->SR1[1U] = 0x1400U;
Checked the esm group2 register and could see these bits (bit 6 and 8) are set. Ideally it should be bit 10 and 12 should be set. Can you explain this behavior?
Also, how to reproduce the address parity error (bit 10 and 12 of esm group 2 register)?
Quick response is highly appreciated.