Part Number:OMAPL138B-EP
Team,
We are using OMAPL138 and DM3730. During its Power-ON reset (POR), both the processor pull down its the GPIO's even with 1K pull-up resistor. Can you please confirm is that behavior of these processor during POR?
In my system, the nTRST pin is pulled down with 4.75K resistor and board reset is tied with RESET (K14) pin in OMAPL138 and SYS_NRESEPWRON (AA10) pin in DM3730.
The Processor GPIO pin is connected with FPGA device reconfiguration (Active low) pin with 1K pull-up resistor. GPIO pin in DM3730 is DSS_DATA1 (AB19) and in OMAPL138 is GP1[4] (G18).
During the Board reset, we want only the processor to go POR and we don't want to re-configure the FPGA. But both the processor GPIO pins are driving LOW during POR and it re-configures the FPGA.
- Datasheet of DM3730 says, High-impedance with an active pulldown resistor (250uA max) for DSS_DATA1 (AB19) during Power-on reset.
- OMAPL138 datasheet says "All pins are tri-stated/High impedance state" during Power-on Reset.
Can you please help us on this?
Thank you.