Hi,
I see in spru732j and spru610c that, an execute packet is allowed to span two fetch packets. But I did not found out a detail description about what the PR and DP stages will act on such a condition.
I show an example in the following figure:
...
inst 1 ; EP1 ; FP1 ; ---------- DC stage
|| inst 2
inst 3 ; EP2 ; ---------- DP stage
|| inst 4
inst 5 ; EP3 ; ---------- PR stage
|| inst 6
|| inst 7
|| inst 8
----------
|| inst 9 ; EP3 (spans FPs) ; FP2 ; ---------- PW stage
|| inst 10
|| inst 11
|| inst 12
inst 13 ; EP4
|| inst 14
|| inst 15
|| inst 16
See, there are two fetch packets FP1 and FP2. The FP1 has three execute packets EP1, EP2 and EP3. The FP2 has two execute packets EP3 and EP4. The execute packet EP3 contains 8 instructions and spans the two fetch packets.
In this cycle, EP1 is moved to DC stage and EP2 is advanced in DP stage. The first part of EP3 in FP1 still stays in PR stage. The whole FP2 is still kept in PW stage.
Then, in the next cycle, what will happen? Will the two parts of EP3 (who spans two fetch packets) be moved to DP/DC/E1 stages one following the other, instructions 5-8 first, then instruction 9-12 follow? Or will the whole execute packet EP3 be moved to DP in the save cycle?
If it is the latter, then how to achieve that? What will happen in the pipeline?
Thanks and best regards,