MSP432E401Y: Host Bus Mode External interface with wait states

Hello all.
I am going to create some module, responsible for TCP/IP connection.
I will be extra pcb inserted to the main pcb.
I am going to use MSP432E401Y for this purpose.
Data exchange with main CPU by shared  SRAM, located on the inserted PCB. So  now I design something like dualportram but with main processor burst mode priority.
So I have questions about  Host Bus Mode with wait cycles.
Unfortunately it is not described obviously in the MSP432E4 SimpleLinkTM Microcontrollers Technical Reference Manual.
Literature Number: SLAU723A. Or may be I did not find  that description.
So questions :
1) How long the IRDY signal can be (How much WAIT cycles are posible). As I understood  maximum  is 8 EPI clock cycles. Is'n it?
2) What happen if IRDY signal takes longer than maximum.
3) What happen if IRDY signal get  active state before start EPI cycle(Write or Read).
Thanks in advance
Best regards
Andrii Shevchuk