I was trying to use the hal code gen to set up my DMM as a GIO, but hal code seems to be a little buggy. So, I reverse engineered my own code based off the texh doc but still cant seem to write any of the ports high.
I think the issue I am having is that when i look at the debuger, my assigned values are not showing up correctly in the pin control memory address. The only PC address that is working is the Dout. I have attatched a screen shot of the memmory.
(Yes i am awear that the enable,sync, and clk are configured as inputs. I am also aware that I tried to write to pins configured as inputs.)
What am i doing wrong?
//My memory address define in dmm reg file
#define dmmREG ((dmmBASE_t *)0xFFFFF700U)
#define dmmPORT ((gioPORT_t *)0xFFFFF770U)
//The following is a snapshot from the dmmInit function.....
/* Determines if pins are uses as input/output (GIO) oR there original functionality */
/* A "1" sets the pin to its original functionality. a "0" sets the pin to GIO (input/output) */
dmmREG->PC0 = 0U /* DMM SYNC */
| (0U << 1U) /* DMM CLK */
| (0U << 2U) /* DATA[0] */
| (0U << 3U) /* DATA[1] */
| (0U << 4U) /* DATA[2] */
| (0U << 5U) /* DATA[3] */
| (0U << 6U) /* DATA[4] */
| (0U << 7U) /* DATA[5] */
| (0U << 8U) /* DATA[6] */
| (0U << 9U) /* DATA[7] */
| (0U << 10U) /* DATA[18] */
| (0U << 11U) /* DATA[19] */
| (0U << 12U) /* DATA[10] */
| (0U << 13U) /* DATA[11] */
| (0U << 14U) /* DATA[12] */
| (0U << 15U) /* DATA[13] */
| (0U << 16U) /* DATA[14] */
| (0U << 17U) /* DATA[15] */
| (0U << 18U); /* DMM ENA */
/* The bits in this register define the direction of the individual module pins when in GIO mode */
/* A "1" sets the pin to be and output, a "0" sets the pin to be an input*/
dmmREG->PC1 = 0U /* DMM SYNC */
| (0U << 1U) /* DMM CLK */
| (1U << 2U) /* DATA[0] */
| (1U << 3U) /* DATA[1] */
| (1U << 4U) /* DATA[2] */
| (1U << 5U) /* DATA[3] */
| (1U << 6U) /* DATA[4] */
| (1U << 7U) /* DATA[5] */
| (1U << 8U) /* DATA[6] */
| (1U << 9U) /* DATA[7] */
| (1U << 10U) /* DATA[18] */
| (1U << 11U) /* DATA[19] */
| (1U << 12U) /* DATA[10] */
| (1U << 13U) /* DATA[11] */
| (1U << 14U) /* DATA[12] */
| (1U << 15U) /* DATA[13] */
| (1U << 16U) /* DATA[14] */
| (1U << 17U) /* DATA[15] */
| (0U << 18U); /* DMM ENA */
/* The bits in this register reflect the digital representation of the voltage level at the module pins. Even if a */
/* pin is configured to be an output pin, the level can be read back via this register. */
/* A "0" is an logic low, "1" is a logic high */
dmmREG->PC2 = 0U /* DMM SYNC */
| (0U << 1U) /* DMM CLK */
| (0U << 2U) /* DATA[0] */
| (0U << 3U) /* DATA[1] */
| (0U << 4U) /* DATA[2] */
| (0U << 5U) /* DATA[3] */
| (0U << 6U) /* DATA[4] */
| (0U << 7U) /* DATA[5] */
| (0U << 8U) /* DATA[6] */
| (0U << 9U) /* DATA[7] */
| (0U << 10U) /* DATA[18] */
| (0U << 11U) /* DATA[19] */
| (0U << 12U) /* DATA[10] */
| (0U << 13U) /* DATA[11] */
| (0U << 14U) /* DATA[12] */
| (0U << 15U) /* DATA[13] */
| (0U << 16U) /* DATA[14] */
| (0U << 17U) /* DATA[15] */
| (0U << 18U); /* DMM ENA */
/* The bits in this register set the pin to logic low or high level if the pin is configured as output */
/* a "0" represents LOW, "1" represents HIGH */
dmmREG->PC3 = 0U /* DMM SYNC */
| (0U << 1U) /* DMM CLK */
| (0U << 2U) /* DATA[0] */
| (0U << 3U) /* DATA[1] */
| (0U << 4U) /* DATA[2] */
| (0U << 5U) /* DATA[3] */
| (0U << 6U) /* DATA[4] */
| (0U << 7U) /* DATA[5] */
| (0U << 8U) /* DATA[6] */
| (0U << 9U) /* DATA[7] */
| (0U << 10U) /* DATA[18] */
| (0U << 11U) /* DATA[19] */
| (0U << 12U) /* DATA[10] */
| (0U << 13U) /* DATA[11] */
| (0U << 14U) /* DATA[12] */
| (0U << 15U) /* DATA[13] */
| (0U << 16U) /* DATA[14] */
| (0U << 17U) /* DATA[15] */
| (0U << 18U); /* DMM ENA */
/*This register allows to set individual pins to a logic high level without having to do a read-modify-write */
/*operation as would be the case with the DMMPC3 register */
/*Writing a zero to a bit will not change the state of the pin*/
/* a "0" does nothing, "1" represents HIGH */
dmmREG->PC4 = 0U /* DMM SYNC */
| (0U << 1U) /* DMM CLK */
| (0U << 2U) /* DATA[0] */
| (0U << 3U) /* DATA[1] */
| (0U << 4U) /* DATA[2] */
| (0U << 5U) /* DATA[3] */
| (0U << 6U) /* DATA[4] */
| (0U << 7U) /* DATA[5] */
| (0U << 8U) /* DATA[6] */
| (0U << 9U) /* DATA[7] */
| (0U << 10U) /* DATA[18] */
| (0U << 11U) /* DATA[19] */
| (0U << 12U) /* DATA[10] */
| (0U << 13U) /* DATA[11] */
| (0U << 14U) /* DATA[12] */
| (0U << 15U) /* DATA[13] */
| (0U << 16U) /* DATA[14] */
| (0U << 17U) /* DATA[15] */
| (0U << 18U); /* DMM ENA */
/*This register allows to set individual pins to a logic high level without having to do a read-modify-write */
/*operation as would be the case with the PC3 register */
/*Writing a "1" to a bit will change the output to a logic low level, writing a zero will not change the state of the pin. */
/* a "0" does nothing, "1" represents LOW */
dmmREG->PC5 = 0U /* DMM SYNC */
| (0U << 1U) /* DMM CLK */
| (0U << 2U) /* DATA[0] */
| (0U << 3U) /* DATA[1] */
| (0U << 4U) /* DATA[2] */
| (0U << 5U) /* DATA[3] */
| (0U << 6U) /* DATA[4] */
| (0U << 7U) /* DATA[5] */
| (0U << 8U) /* DATA[6] */
| (0U << 9U) /* DATA[7] */
| (0U << 10U) /* DATA[18] */
| (0U << 11U) /* DATA[19] */
| (0U << 12U) /* DATA[10] */
| (0U << 13U) /* DATA[11] */
| (0U << 14U) /* DATA[12] */
| (0U << 15U) /* DATA[13] */
| (0U << 16U) /* DATA[14] */
| (0U << 17U) /* DATA[15] */
| (0U << 18U); /* DMM ENA */
/*These bits configure the pins in push-pull or open-drain functionality. If configured to be open-drain, the
module only drives a logic low level on the pin. An external pull-up resistor needs to be connected to the
pin to pull it high when the pin is in high-impedance mode.*/
dmmREG->PC6 = 0U /* DMM SYNC */
| (0U << 1U) /* DMM CLK */
| (0U << 2U) /* DATA[0] */
| (0U << 3U) /* DATA[1] */
| (0U << 4U) /* DATA[2] */
| (0U << 5U) /* DATA[3] */
| (0U << 6U) /* DATA[4] */
| (0U << 7U) /* DATA[5] */
| (0U << 8U) /* DATA[6] */
| (0U << 9U) /* DATA[7] */
| (0U << 10U) /* DATA[18] */
| (0U << 11U) /* DATA[19] */
| (0U << 12U) /* DATA[10] */
| (0U << 13U) /* DATA[11] */
| (0U << 14U) /* DATA[12] */
| (0U << 15U) /* DATA[13] */
| (0U << 16U) /* DATA[14] */
| (0U << 17U) /* DATA[15] */
| (0U << 18U); /* DMM ENA */
/*The bits in register control the pullup/down functionality of a pin. The internal pullup/down can be enabled
or disabled by this register. The reset configuration of these bits is device implementation dependent.
Please consult the device datasheet this information*/
/*A '1' disables pull up/pull down functionality, 0 enables */
dmmREG->PC7 = 0U /* DMM SYNC */
| (0U << 1U) /* DMM CLK */
| (0U << 2U) /* DATA[0] */
| (0U << 3U) /* DATA[1] */
| (0U << 4U) /* DATA[2] */
| (0U << 5U) /* DATA[3] */
| (0U << 6U) /* DATA[4] */
| (0U << 7U) /* DATA[5] */
| (0U << 8U) /* DATA[6] */
| (0U << 9U) /* DATA[7] */
| (0U << 10U) /* DATA[18] */
| (0U << 11U) /* DATA[19] */
| (0U << 12U) /* DATA[10] */
| (0U << 13U) /* DATA[11] */
| (0U << 14U) /* DATA[12] */
| (0U << 15U) /* DATA[13] */
| (0U << 16U) /* DATA[14] */
| (0U << 17U) /* DATA[15] */
| (0U << 18U); /* DMM ENA */
//enable the pull up
dmmREG->PC8 = 1U /* DMM SYNC */
| (1U << 1U) /* DMM CLK */
| (0U << 2U) /* DATA[0] */
| (0U << 3U) /* DATA[1] */
| (0U << 4U) /* DATA[2] */
| (0U << 5U) /* DATA[3] */
| (0U << 6U) /* DATA[4] */
| (0U << 7U) /* DATA[5] */
| (0U << 8U) /* DATA[6] */
| (0U << 9U) /* DATA[7] */
| (0U << 10U) /* DATA[18] */
| (0U << 11U) /* DATA[19] */
| (0U << 12U) /* DATA[10] */
| (0U << 13U) /* DATA[11] */
| (0U << 14U) /* DATA[12] */
| (0U << 15U) /* DATA[13] */
| (0U << 16U) /* DATA[14] */
| (0U << 17U) /* DATA[15] */
| (1U << 18U); /* DMM ENA */