In this application, the UCC28950 is normally used as an unregulated full-bridge HV DC-DC switch controller. Slow start is used to reduce potential stress on switches due to small output inductors at start (or hiccough re-entry from limiting). The EA is only used to enforce a similar slow start under system reset requirements.
I find, however, that the CS reaction to peak current limit settings introduces major volt-second imbalances, as the logic switches from near-zero to full duty in half-frequency increments. This was demonstrated in one unit due to abnormally high internal slope settings triggering the peak detection early.
It looks like a peak detection in one phase period caused the following phase (alone) to be cancelled. Such a condition ramps the full bridge isolator into 3xnormal peak flux in a single event.
The currents generated under saturation are non-linear from one period to the next and are actually preserved under the zero-power-transfer protective phasing. In this application, a single missing period, generated by a peak detection seems oddly reinforcing.
Is there any way of making the peak current limit (ie a fault) enforce a definite SS cycle?
The usual problem with images here. Will follow up with link.