Part Number:ADS8556
Hi PRADC Team,
Happy Friday!
I am posting these questions on behalf of my customer.
(1)
When does the ADS8556 latch its configuration mode? Specifically on pins HW/SW (pin 62), Refen/wr (63) and various DBx inputs such as DB14/REFbufen (1).
Can a configuration mode obtained at POR be changed later with a secondary reset assertion and negation?
(2)
While using ADS8556 in hardware mode, parallel mode with internal reference with a static DC signal at its input, what can cause the ADC to output all 0s during parallel read cycle shown in figure3 of the datasheet?
I know for certain that the logic 0 is driven by ADC since bus value is different prior to the read cycle. I do not expect a partial shutdown or power saving to take place since device responds with BUSY assertion and negation as expected.
Thank you very much!
Lauren