Part Number:TMS320C6652
Tool/software: Code Composer Studio
Hi,
First, I created a firmware that works with the evaluation board (EVM of C6657). This worked fine.
So, as a next step, I made our prototype board which has one "C6652" device and,
I changed the firmware of C6657 to fit the C6652(PLL settings, Clock settings etc... ).
After that, These are FW writing procedure(using CCSv8.3).
1. Power on the prototype board, and open the CCS.
2. Connect "XDS200" to the prototype board with JTAG.
3. Open the Target Configuration File, and set as the follow.
- Connection: Texas Instruments XDS2xx USB Debug Probe
- Board or Device: TMS320C6652
- Target Configuration(Advanced Setup): initialization script -> C6652.gel(The details will be available later)
- Test Connection -> OK
4. Debug Start (Load Program)
When I start to load our FW, bootmode is "no boot".
Therefore I load an initialization script(c6652.gel) file. this file is based on evmc6657l.gel which is provided by TI.
The difference between them is currently only about "PLL Settings".
c6652.gel loading works but, After "XMC Setup ... Done", CCS Console outputs errors as the follow.
C66xx_0: GEL Output: Setup_Memory_Map...
C66xx_0: GEL Output: Setup_Memory_Map... Done.
C66xx_0: GEL Output:
Connecting Target...
C66xx_0: GEL Output: DSP core #0
C66xx_0: GEL Output: C6657L GEL file Ver is 1.00399995
C66xx_0: GEL Output: Global Default Setup...
C66xx_0: GEL Output: Setup Cache...
C66xx_0: GEL Output: L1P = 32K
C66xx_0: GEL Output: L1D = 32K
C66xx_0: GEL Output: L2 = ALL SRAM
C66xx_0: GEL Output: Setup Cache... Done.
C66xx_0: GEL Output: Main PLL (PLL1) Setup ...
C66xx_0: GEL Output: PLL in Bypass ...
C66xx_0: GEL Output: PLL1 Setup for DSP @ 600.0 MHz.
C66xx_0: GEL Output: SYSCLK2 = 200.0 MHz, SYSCLK5 = 120.0 MHz.
C66xx_0: GEL Output: SYSCLK8 = 9.375 MHz.
C66xx_0: GEL Output: PLL1 Setup... Done.
C66xx_0: GEL Output: Power on all PSC modules and DSP domains...
C66xx_0: GEL Output: Power on all PSC modules and DSP domains... Done.
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ...
C66xx_0: GEL Output: DDR3 PLL Setup... Done.
C66xx_0: GEL Output: DDR3 Init begin (1333 auto)
C66xx_0: GEL Output: XMC Setup ... Done
C66xx_0: Trouble Writing Memory Block at 0x210000d8 on Page 0 of Length 0x4: (Error -1060 @ 0x210000D8) Device is not responding to the request. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 8.0.903.2)
C66xx_0: GEL: Error while executing OnTargetConnect(): Target failed to write 0x210000D8
at *((unsigned int *) (0x21000000+0x000000D8))=0x80000000 [C6652.gel:241]
at ddr3_setup_auto_lvl_1333(0) [C6652.gel:783]
at Global_Default_Setup_Silent() [C6652.gel:510]
at OnTargetConnect()
C66xx_0: Trouble Reading Register ControlRegisters.CSR: (Error -1060 @ 0x41) Device is not responding to the request. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 8.0.903.2)
C66xx_0: GEL Output: Invalidate All Cache...
C66xx_0: Trouble Writing Memory Block at 0x1845028 on Page 0 of Length 0x4: (Error -1060 @ 0x1845028) Device is not responding to the request. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 8.0.903.2)
C66xx_0: GEL: Error calling OnPreFileLoaded(): Target failed to write 0x01845028
C66xx_0: Trouble Reading Memory Block at 0x800000 on Page 0 of Length 0x4: (Error -1060 @ 0x64) Device is not responding to the request. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 8.0.903.2)
C66xx_0: File Loader: Verification failed: Target failed to read 0x00800000
This error was output within "ddr3_setup_auto_lvl_1333" function.
and, applicable place is "DDR_SDRFC = 0x0000144F; //Refresh rate = (7.8*666MHz)" .
What is the reason about this case?
How should we check as a next step?
[Supplementary explanation]
Our prototype board has two "N25CC128M16JR-EK(DDR3 devices)" instead of "MT41J128M16HA-125"(EVM devices).
We connected each pins same as EVM's reference design.
Best regards,