Part Number:AWR1243
Hi, TI experts
I am working on a project that cascades 4 AWR1243s. The circuit are configured as:
1) all chips (master of slave) are set to HWTRIG (hardware trigger) mode, and all SYNC_IN1 are driven by one identical periodic pulse;
2) the LO of the master chip are driven by a RF amplifier and fed to all 4 chips;
3) the clock inputs of all chips are driven by fanout of a TCXO clock.
4) the CSI-2 outputs are configured as 2-lane, and connected directly to the NVIDIA Jetson TX2, via a adaptor. The 6 channel 2-lane CSI-2 driver is modified based on a existing camera driver.
But the board outputs nothing from CSI-2 interface. I tried only master chip with success, either in HWTRIG or SWTRIG mode, but failed with 2-chip or 4-chip cascade configuration.
Here are my questions:
1) Is the above configuration feasible?
2) Which steps should I follow? I tried the steps listed in section 5.22.2 <AWR1xxx_interface_control.pdf>, but with no success.
The log is attached. Hope it will be helpful.
Qian(Please visit the site to view this file)
