Part Number:PGA302
Hi professional,
Our customer has questions for PGA302, PGA305, PGA900.
1.PGA302
- As datasheet mentioned, Output sample rate is typ 96us. is this meaning that ADC's sample rate is 96us?
- this specification's test condition was written "Sample period control bit = 0b00". However I couldn't find "Sample period control bit" on the other page. What is "Sample period control bit"?
- Is the actual output rate determined by decimation filter setting?
- Which register can set the decimation filter?
- Simplified Block Diagram has I2C block. But Functional Block Diagram don't has I2C. Could you explain about constitution of I2C block?
- I couldn't found specification for I2C interface(i.e. data rate). Could you provide it?
2.PGA305
- The datasheet said that "Output rate" is "Typ 512us" in the "Operating Characteristics". however this said "a 16-bit ADC at a 7.8-kHz(128us) output rate" in 7.1 Overview. So this description make confusion for me. Would you explain about meaning of Output rate and why this device has 2 type of output rate? By the way My understanding of response time is that the time from the input of the signal to the output of the data. is this correct?
3.PGA900
- In the case of PGA900 datasheet Output sample period on Operating Characteristics is 64us or 128us. And Output rates on "7.1. Overview" is 7.8kHz(128us) or 15.6kHz(64us). Do these mean the same thing?
- Are the meaning "Output sample period" and "Output rate" ADC's sample rate?
- Dose "Sample period control bit" same as "PADC_ DECI_RATE"?
4.General question
- PGA302, PGA305 and PGA900 looks like similar products. However they use various terms and definitions.(i.e. Output rate, Output sample period) So our customer guessed there product has big difference. thus their datasheet used various terms and definitions. Is this correct? or is this just orthographical variants?
I'm looking forward hearing from you.
Best Regards,
Kazuki Kuramochi