TMS570LC4357: How does _errata_SSWF021_45_both_plls introduced by HALCoGen 4.7.1 function in the following configuration?

Part Number:TMS570LC4357

We have a custom board using TMS570LC4357 with the following connections -- shown in the picture pasted at the end of this query.

In the configuration we are testing, R31 is absent and hence there is no OSCIN input to the MCU.

The clock comes into GIOA5/EXTCLKIN. HALCoGen generates a call to _errata_SSWF021_45_both_plls(PLL_RETRIES) from _c_int00 if the reset source is POWERON_RESET.

void _c_int00(void)
{
    register resetSource_t rstSrc;
/* USER CODE BEGIN (5) */
/* USER CODE END */

    /* Initialize Core Registers to avoid CCM Error */
    _coreInitRegisters_();
    
    /* Initialize Stack Pointers */
    _coreInitStackPointer_();

    /* Reset handler: the following instructions read from the system exception status register
     * to identify the cause of the CPU reset.
     */
    rstSrc = getResetSource();
    switch(rstSrc)
    {
        case POWERON_RESET:
        /* Initialize L2RAM to avoid ECC errors right after power on */
        _memInit_();

        /* Add condition to check whether PLL can be started successfully */
        if (_errata_SSWF021_45_both_plls(PLL_RETRIES) != 0U)
        {
            /* Put system in a safe state */
            handlePLLLockFail();
        }
        
/*SAFETYMCUSW 62 S MR:15.2, 15.5 <APPROVED> "Need to continue to handle POWERON Reset" */
        case DEBUG_RESET:
        case EXT_RESET:

.......

Now this _errata function seems to assume the presence of OSCIN.

uint32 _errata_SSWF021_45_both_plls(uint32 count)
{
    uint32 failCode,retries,clkCntlSav;

    /* save CLKCNTL */
    clkCntlSav = systemREG1->CLKCNTL;
    /* First set VCLK2 = HCLK */
    systemREG1->CLKCNTL = clkCntlSav & 0x000F0100U;
    /* Now set VCLK = HCLK and enable peripherals */
    systemREG1->CLKCNTL = SYS_CLKCNTRL_PENA;
    failCode = 0U;
    for(retries = 0U;(retries < count); retries++)
    {
        failCode = 0U;
        /* Disable PLL1 and PLL2 */
        failCode = disable_plls(SYS_CLKSRC_PLL1 | SYS_CLKSRC_PLL2);
        if(failCode != 0U)
        {
            break;
        }

        /* Clear Global Status Register */
        systemREG1->GBLSTAT = 0x00000301U;
        /* Clear the ESM PLL slip flags */
        esmREG->SR1[0U] = ESM_SR1_PLL1SLIP;
        esmREG->SR4[0U] = ESM_SR4_PLL2SLIP;
        /* set both PLLs to OSCIN/1*27/(2*1) */
        systemREG1->PLLCTL1 = 0x20001A00U;
        systemREG1->PLLCTL2 = 0x3FC0723DU;

........

So what happens in our configuration? Does this function fail, causing the MCU to go into a "safe" state?

The handlePLLLockFail() is just an infinite while loop .. while(1) {}

Are we supposed to just remove this check from HALCoGen generated code in our configuration?

All help in understanding this situation is much appreciated.

Thank you

Subu