Part Number:DAC38RF80EVM
Currently, I am trying to configure the various output clocks at our disposal from the LMK04828 clock synthesizer/jitter cleaner and am having a few issues. I've attached a screen shot of the GUI page where I believe the issue may be occurring: 
I've been trying initially to produce an output at CLKout 4 since that is connected to SMA J24 just to verify the LMK is working properly before hooking up our FPGA. So far, I have been able to produce an output signal. I've made to sure to uncheck the "group powerdown" checkbox and adjusted the settings seen above. Am I missing something?
I have an input clock at the DACCLK+/- but currently don't have the LMK CLock input at 1/4 of the DACCLK sampling freq. Would that be why, or does something else need changed or some other action have to take place?
Thanks,
Jared