Hello:
Now I have three urgent questions about C6670 AIF2, and I need your help.
Firstly, my platform is described as follows:C6670's AIF2 interface connect with FPGA, OBSAI protocol running in AIF2 interface, the link rate is 8x(6.144Gbps), LTE with 20M bandwidth and 4 AxCs.
Secondly, three questions are as follows:
(1)With Normal Cyclic Prefix, every timeslot(0.5ms) has 7 LTE symbols. Can I define 3 MONO_TX_COMPLETE_Qs each AxC using for TX circularly in L2(or MSMC), not define 7, in order to save L2(or MSMC) memory size? And the same for MONO_RX_FDQ?
(2)As the above (1), I define 3 MONO_RX_FDQs each AxC using for RX circularly in L2(or MSMC). I can consecutively and rightly receive AxC datas, and transfer these datas from L2 to DDR3 using EDMA3. But for TX, when I transfer datas from DDR3 to L2 using EDMA3, then packaged and pushed to MONO_TX_Q, the data can't TX out rightly, in other words, the FPGA can't receive the datas rightly (the FPGA code is no problem). I don't know why,can you tell me some probably reasons?
(3)In order to solve the question (2), we have done many experiments. Now we find that if we package the datas only once and push it consecutively, it operate well. But if we package one datas and push it, then package one another and push, repeating this for many times,it will be wrong. The number "tx_count" will be a very large number, about tens of thousand. (tx_count = get_descriptor_count(MONO_TX_Q0) ) . I think the reason is the PKTDMA doesn't run well after I push the package to MONO_TX_Q, do you agree? and how to solve it?
The questions are urgent, and I hope you can help me to solve them as quckily as possible. Thank you very much!