Part Number:TM4C1294KCPDT
I ran into some issues with the watchdog timer reset not working following loss of clock. I've got everything working now, but that behavior was quite unexpected and I've got some questions about reset.
I'm using the PLL is used to derive SYSCLK from the MOSC, which is provided by an external single-ended source that may stop.
I found that watchdog module 1 (the one clocked off PIOSC) and the RST pin where both unable to reset the device after the external clock stopped. I was able to make them work by changing the reset types in RESBEHAVCTL from the default simulated POR to a system reset. Is this the expected behavior? If so, it would be nice if the workaround for errata SYSCTL#03 mentioned the need to change the reset type. What is the difference between the simulated POR sequence and a system reset?