Part Number:CC1101
After having received a valid message on 915MHZ, the frequency was changed to 905MHZ, RX FIFO flushed, and RX enabled. I would have expected the PLL Lock indicator to show that the PLL was locked in approximately 75uS according to the datasheet (no calibration performed). However, it took 144.5uS, and 166.25uS for the PLL Lock indicator to show lock for 915MHZ, and 905MHZ respectively. This is using a GPIO line for PLL lock indicator.
What are the variables that would cause this lock indicator to take longer than expected ? From the datasheet, one would assume that the lock time indicator is nearly fixed at 75uS(Please visit the site to view this file) (assuming that it locks at all).
Logic analyzer pictures are attached.
Thanks.