OMAPL138B-EP: Inconsistent interrupt latency INT4 & INT5 of Dsp core

Part Number:OMAPL138B-EP

Hi,

Iam using OMAPL138 with 456Mhz clock speed.Here iam using two interrupts 

1.GPIO Interrupt (C674X_MASK_INT4 )

IntRegister(C674X_MASK_INT4, GPIOIsr);

IntEventMap(C674X_MASK_INT4, SYS_INT_GPIO_B8INT);

IntEnable(C674X_MASK_INT4);

GPIO pin is configured for rising edge interrupt

2.EDMA3 Interrupt(C674X_MASK_INT5 )

 IntRegister(C674X_MASK_INT5, Edma3ComplHandlerIsr);

IntEventMap(C674X_MASK_INT5, SYS_INT_EDMA3_0_CC0_INT1);

 IntEnable(C674X_MASK_INT5);

EDMA is configured for SPI interrupt

In GPIO ISR iam enabling SPI DMA interrupt and clearing GPIO interrupt and event and in DMA ISR iam collecting 17bytes of data using SPI and do some calculation on samples 

Here GPIO isr contents taking 160nS and DMA ISR is taking 8.6uS and we used another GPIO pin inside GPIO ISR to chk the interrupt latency by making it logic high at the start of ISR.As per document Interrupt latency is 13Cycles

Problem statement:

Case 1:

Do nothing in main loop after initilization 

Here iam getting consistent interrupt latency of around 1.5us

main()

//init code

//enable both interrupts

while(1)

{//do nothing

}

Case 2:

Do some simple data manipulation  in main loop

Here iam getting inconsistent interrupt latency 1.6us to around 6us.Why this is happening.Even if we do anything in main loop ,it should get interrupted with consistent interrupt latency

I think In worst case,if we do some complex calculation in main loop, still this variation in latency is not acceptable.

main()

//init code

//enable both interrupts

while(1)

{//do data manipulation 

}

Please let me know why  there is so much variation in latency

Regards,

Satheesh