Hello,
I posted this problem back in December and by some magic combination I was able to get it work.
http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/233503/824058.aspx#824058
However, I am redo the same code with some slight differences and the problem is back! I can't get this section of code to invalidate the value in L1d cache.
The pseudo code is this - CORE0 sets a flag (in a struct) to indicate to CORE1 that it is time to start working. CORE1 reads the variable from the struct and patiently waits until the flag is set. After every read, it sleeps for a bit and then invalidated cache and checks again. I do not have L2 cache enabled, only L1.
#pragma DATA_ALIGN(128)
#pragma DATA_SECTION(".srioSharedMem")
volatile TrackerSharedMemoryStruct far trackerMem;
1. while((trackerMem.asscVars.assocStartFlag & (CORE0_ASSOC_TASK << CORE_NUM)) == 0)//wait for your flag to be active.
{
2. Task_sleep(ASSOC_SLEEP_DELAY);
3. CACHE_invL1d((void *)&trackerMem, 1024,CACHE_WAIT);
}
Like before, the emulator is showing me that it is correctly written in MSMCSRAM and that CORE1 is just not seeing it correctly. Using line numbers as reference, Line 1 reads the flag and it is zero. The task sleeps, line 3 invalidates the entire structure (which is volatile and aligned). If I break at line 3 and check the memory, I can see the flag is set to a value. then when I loop back around to Line 1, the value is zero again! I also can see that CORE0 set the flag and wrote back its cache.
Please advise. I didn't really understand why the solution worked the first time and it obviously wasn't viable because a small change in the memory map broke it again!
Things I have tried:
- volatile and far -> no improvement
- DATA_ALIGN 64, 128, 512 -> none worked
- Cache invalidate just the variable with size 128 (CACHE_invL1d ((void *)&trackerMem.asscVars.assocStartFlag, 128,CACHE_WAIT))
- The structure is only 304 bytes, so I have tried to invalidate every size, 128, 256, 512, 1024.
- I disabled cache in MSMCSRAM. This solves the problem but I don't want to do that, this structure is used all the time. Once the cores read the variables once, I would prefer them to cache them!
Thanks for any help! This is just so silly. I have similar loops all throughout my code. 2 of them are working. This one is not and there are 2 untested because they are after this loop. All 5 worked before the memory map got changed (what I mean is I deleted some unused variables that were existing in MSMCSRAM).
Brandy