Part Number:TFP401A
Hello LHS Team,
Customer is interfacing TFP401A + DS90C387A to an OLED display per TI App Note slla325 and is having issues. A brief synopsis from the customer is below:
We have a first design that is not working and what is worst: we are not sure about what is the real problem. We can watch fuzzy images and only when we reduce the frame rate and therefore the pixel clock for dual channel LVDS to around 60Mhz instead of 74.25Mhz (theoretical for 1080p@60hz).
We suspect about several causes...
1. Recently we found out from the display mfg. that the first pixel is even and not odd, so the design is wrong and the bits are swapped. We are not sure what implies this fail because it would be expected that the image be erroneous (order pixels swapped) but not that there image not be sharp. Am I wrong?. In your slla325c application note, page 5, you recommend to swap in this case QO[0:23] and QE[0:23] when working with "even-first" serialization regards the figure 4 in same page. Won't be easier to swap the serialized lanes instead the RGB bits, I mean A[0:3] and A[4:7]?
2. We are not really sure about the previous assumption since we don't find the specification in the datasheet about the maximum delay between the odd and even clocks at the output of Ds90c387a and in our display the input is limited to 500ps between even clock (expected first in the time) and odd clock (expected at the same time or later in the time). Could you clarify this point and confirm what is the maximum delay between Ds90c387a output clocks and which one comes out first?
3. The LVDS voltage levels are slightly different: common mode voltage meets but Ds90c387a differential voltage is greater than the expected at the input of the display. Not sure how serious is this point.
I hope you could give us some hints about if we are in the right way or if there is a real obstacle to make work our display with Tfp401a + Ds90c387a.
