Part Number:TMS570LS3137
Hello Forum,
I’am using a TMS570LS3137DZWT and developing an EN50129 Application that is running more than 24h. Therefore I want to check the presence of a working SRAM ECC. I used SPNA126 and Halcogen 4.07 as starting point.
The Data Abort Handler is used to check an confirm the presence of the double bit faults (esmr3)
Following steps are performed:
1.) Disable RAMECC for B0TCM and B1TCM;
2.) Double Bit flip in ECC RAM; [#define tcramA2bitError (*(volatile uint32 *)(0x08400010U)); #define tcramB2bitError (*(volatile uint32 *)(0x08400018U))]
3.) Enable RAMECC for B0TCM and B1TCM;
4.) Read fault location for B0TCM from RAM [#define tcramA2bit (*(volatile uint64 *)(0x08000010U)); #define tcramB2bit (*(volatile uint64 *)(0x08000018U))]
5.) --> Data abort Handler confirms esmr3 bit 3 (uncorrectable ECC error on B0TCM)
6.) Read fault location for B1TCM from RAM (
7.) --> Data abort Handler should confirms esmr3 bit 5 (uncorrectable ECC error on B1TCM), but esmr1, esmr2, esmr3 are all 0, nothing to clear.
My test function looks up to now
...
volatile uint64 ramread = 0U;
volatile uint32 regread = 0U;
//uint32 tcram1ErrStat, tcram2ErrStat = 0U;
uint64 tcramA1_bk = tcramA1bit;
uint64 tcramB1_bk = tcramB1bit;
uint64 tcramA2_bk = tcramA2bit;
uint64 tcramB2_bk = tcramB2bit;
/* Clear RAMOCUUR before setting RAMTHRESHOLD register */
tcram1REG->RAMOCCUR = 0U;
tcram2REG->RAMOCCUR = 0U;
/* Set Single-bit Error Threshold Count as 1 */
tcram1REG->RAMTHRESHOLD = 1U;
tcram2REG->RAMTHRESHOLD = 1U;
/* Enable single bit error generation */
tcram1REG->RAMINTCTRL = 1U;
tcram2REG->RAMINTCTRL = 1U;
/* Enable writes to ECC RAM, enable ECC error response */
tcram1REG->RAMCTRL = 0x0005010AU;
tcram2REG->RAMCTRL = 0x0005010AU;
// PART 2
// coreDisableRamEcc
asm("MRC p15,#0, r1, c1, c0, #1");
asm("MVN R0,#0x1<<26"); //; B0TCM ECC check disable
asm("AND R1 ,R1, R0");
asm("MVN R0,#0x1<<27"); //; B1TCM ECC check disable
asm("AND R1 ,R1,R0");
asm("DMB");
asm("MCR p15,#0, r1, c1, c0, #1");
asm("ISB"); // ; To ensure the write before proceeding
asm("MRC p15, #0, r1, c9, c12, #0");
asm("MVN R0,#0x00000010"); //; Disable export of the events in PMNC
asm("AND R1 ,R1,R0");
asm("DMB");
asm("MCR p15, #0, r1, c9, c12, #0");
asm("ISB"); //; To ensure the write before proceeding
// asm("MOV PC, lr");
/* Force a double bit error in both the banks */
tcramA2bitError ^= 3U;
tcramB2bitError ^= 3U;
// coreEnableRamEcc
asm("MRC p15,#0,r1,c9,c12,#0"); // Reading secondary Aux secondary Reg.
asm("ORR r1, r1, #0x00000010");
asm("DMB");
asm("MCR p15,#0,r1,c9,c12,#0"); //; Enable export of the events in PMNC
asm("ISB"); //; To ensure the write before proceeding
asm("MRC p15, #0, r1, c1, c0, #1");
asm("ORR r1, r1, #0x1 <<26"); //; B0TCM ECC Check Enable
asm("ORR r1, r1, #0x1 <<27"); //; B1TCM ECC Check Enable
asm("DMB");
asm("MCR p15, #0, r1, c1, c0, #1");
asm("ISB");
/* Read the corrupted data to generate double bit error */
ramread = tcramA2bit; // #define tcramA2bit (*(volatile uint64 *)(0x08000010U))
ramread = tcramB2bit; // #define tcramB2bit (*(volatile uint64 *)(0x08000018U))
Q1: is the above ECC enable code correct ? (In Document SPNA126; Chapter 3.3.2 (Steps to Disable ECC) the code for _DISABLE_ECC_R4_RAM is incomplete, so I’am not sure If coreEnableRamEcc is correct.
Q2: is enabling the ECC checks correct ?
Q3: Why reading from a faulty B0TCM Address works properly, (esmr3 data Abort error occurs)? Reading from B1TCM (tcramB2bitError) causes a data abort without esmr3 error, so in the data abort Handler (from halcogen 4.07) no noRAMerror is reported.
Q4: Is this problem related to following post:
regards
Lorenz