Compiler/TMS320TCI6618: C66 MSMC non Cache read cycles penalty

Tool/software: TI C/C++ Compiler

Hi,

I am accessing MSMC non cached memory. According to document sprabh2a.pdf , MSMC non cached memory is having penalty of 12 cycles.

Since I am accessing data 139 *256 bits(_mem8_const) , I am seeing penalty of 9000 cycles instead of 6672 cycles[12 * 4 * 139 according to sprabh2a.pdf]

Please find the code below:

tPayload -- > Pointing to MSMC non cached memory
tempData -- > Pointing to L2_ISRAM

Header = TimeStampTable[hdrCount];

#pragma MUST_ITERATE(1,139,1);
for(loopCount = 0; loopCount < pairLoop; ++loopCount)
{

Value1 = _mem8_const(tPayload++);
Value2 = _mem8_const(tPayload++);
Value3 = _mem8_const(tPayload++);
Value4 = _mem8_const(tPayload++);

#if 1
hdrFlag = ( _cmpeq4(_loll(Value1), 0) &
_cmpeq4(_hill(Value1), 0) &
_cmpeq4(_loll(Value2), 0) &
_cmpeq4((_hill(Value2) & MASK), Header));
#else
hdrFlag = ( _cmpeq4(_hill(Value1), 0) &
_cmpeq4(_loll(Value1), 0) &
_cmpeq4(_hill(Value2), 0) &
_cmpeq4((_loll(Value2) & MASK), Header));
#endif

if(hdrFlag == 15)
{
hdrCount++;

*tempData++ = Value3;
*tempData++ = Value4;

temp = _cmpeq2(hdrCount, 0xffff005f) - 1;
hdrCount = hdrCount & temp;
countData++;
Header = TimeStampTable[hdrCount];
}
}

Please help in understanding why 3000 cycles are taken extra and also help in mitigating the issue.

Note: Above loop takes only 3300 cycles when both tempData and tPayload are in L2_ISRAM memory.

Regards

Shreyas N