Part Number:TMS570LC4357
Dear Support,
I am confused after having read the SLVSDJ1A (Datasheet of the TPS65381A-Q1) voltage safety supervisor for the TMS570LC4357. On page 103, it is mentioned that the TMS570 communicates with the TPS over MibSPI 1, 3 or 5. Why should the other MibSPI 2 and 4 not be suited? I do not see any reason for this and would prefer to use MibSPI2 to do it. Could you explain the signification of this block diagram and further explain also why the Chip Selects seems also to be restricted to 3..0?
Finally, on page 34 there is another surprising statement in the NOTE: why is the SDO pin not high-Z when the DIAG_OUT MUX is enabled? I do not see any technical reason having the SDO pin low impedance when the CS is high. For what is this chosen configuration ny TI good for? I did not find any configuration until now in which it would help. But I am sure that there must be a reason. Where can I find the explanation?
Thanks in advance.
Best regards
Vincent