Do we have C6457 Throughput App Note similar to the one for C6474 (link here)?
I am trying to get real (as opposed to theoretical) performance numbers for SRIO on C6457 and associated test setup information and source code.
We are seeing lower performance than we would like and want to see what is possible before trying to optimize; from reading data-manuals and e2e posts I have learned that performance can be a function of
1) Transfer size: The larger the better as smaller transfers are challenged by overhead accounting for larger % of transfer, and possibly gaps between transfers as it takes time to write SRIO configuration registers
2) DMA burst size alignment: Again small transfers may incurr same delay thru DMA as a larger 64-bit transfer hence at a disadvantage.
3) transfer packet type (NWRITE_R vs NWRITE)
However, it would still be helpful to know what is realistically possible before attempting to optimize.
Thank you in advance,
Juan