Part Number:TPS61032
Hello-
I'm laying out the TPS61032RSA which has the QFN package and would like to see if someone can help me by reviewing my layout. I looked at the EVM and datasheet, but could only find example layouts for the TSSOP packages.
I am having to make some design compromises in order to make it all work. Since the switch node pin is in between the PGND and VOUT pins, I have to chose between maintaining an uninterrupted GND pour between the input and output caps, or keeping the SW node all on the same layer. I think I have a pretty good layout based on the layout guidelines in the datasheet, but wanted to get another set of eyes on it. I'm using a 4-layer board, with red being top, green being a ground plan at layer 2, blue being SYS_VBAT on layer 3, and blue being bottom layer which is the layer that connects the two switch node vias.
Here are the schematic and layout images.:
Thanks!
Dave