SMOMAPL138B-HIREL: Read Timing Analysis

Part Number:SMOMAPL138B-HIREL

Hi there,

We are trying to perform read timing analysis for EMIFA Asynchronous Memory Interface. We are having trouble showing that we have enough data hold time. The NOR flash device we are interfacing to has an output hold time of 0ns (zero) from the time /OE goes high. The hold time requirement for the SMOMAPL138B-HiRel processor is also 0ns. Since the processor samples the data at the same time it drives /OE high (rising edge of EMA_CLK) its difficult to show positive timing margin. Normally there is a parameter in processor datasheets for internal clock (EMA_CLK in this case) to signal output delay. In this case I'm looking for EMA_CLK to /EMA_OE minimum time. This normally helps to achieve the required timing margin... but we can't see it in the datasheet.

We would appreciate some help finding the missing parameter or any other suggestions you may have.

Regards,

Matthew