CCS/MSP430F5359: Porting Functions to Initialize the UCS/FLL from msp430f5438a to msp430f5359

Part Number:MSP430F5359

Tool/software: Code Composer Studio

Hello, 

I'm trying to port function to initialize the UCS/FLL from msp430f5438a to msp430f5359 for audio PWM, here is the attached code. The audio code works fine for  msp430f5438a but not for the  msp430f5359. what are the changes i need to make in the attached code so that it will work for msp430f5359.

#include "msp430.h"
#include "hal_ucs.h"

void LFXT_Start(uint16_t xtdrive)
{
    // If the drive setting is not already set to maximum
    // Set it to max for LFXT startup
    if ((UCSCTL6 & XT1DRIVE_3) != XT1DRIVE_3){
        UCSCTL6_L |= XT1DRIVE1_L + XT1DRIVE0_L;                 // Highest drive setting for
                                                                // XT1startup
    }

    while (UCSCTL7 & XT1LFOFFG){                                // Check LFXT1 fault flag
        UCSCTL7 &= ~(XT1LFOFFG);                                // Clear LFXT1 fault flag

        // Clear the global fault flag. In case the LFXT1 caused the global fault flag to get
        // set this will clear the global error condition. If any error condition persists,
        // global flag will get again.
        SFRIFG1 &= ~OFIFG;
    }

    UCSCTL6 = (UCSCTL6 & ~(XT1DRIVE_3)) | (xtdrive);            // set requested Drive mode
}


void Init_FLL_Settle(uint16_t fsystem, uint16_t ratio)
{
    volatile uint16_t x = ratio * 32;

    Init_FLL(fsystem, ratio);

    while (x--){
        __delay_cycles(30);
    }
}

void Init_FLL(uint16_t fsystem, uint16_t ratio)
{
    uint16_t d, dco_div_bits;
    uint16_t mode = 0;

    // Save actual state of FLL loop control, then disable it. This is needed to
    // prevent the FLL from acting as we are making fundamental modifications to
    // the clock setup.
    uint16_t srRegisterState = __get_SR_register() & SCG0;

    d = ratio;
    dco_div_bits = FLLD__2;                                     // Have at least a divider of 2

    if (fsystem > 16000){
        d >>= 1;
        mode = 1;
    }
    else {
        fsystem <<= 1;                                          // fsystem = fsystem * 2
    }

    while (d > 512){
        dco_div_bits = dco_div_bits + FLLD0;                    // Set next higher div level
        d >>= 1;
    }

    __bis_SR_register(SCG0);                                    // Disable FLL

    UCSCTL0 = 0x0000;                                           // Set DCO to lowest Tap

    UCSCTL2 &= ~(0x03FF);                                       // Reset FN bits
    UCSCTL2 = dco_div_bits | (d - 1);

    if (fsystem <= 630)                                         //           fsystem < 0.63MHz
        UCSCTL1 = DCORSEL_0;
    else if (fsystem <  1250)                                   // 0.63MHz < fsystem < 1.25MHz
        UCSCTL1 = DCORSEL_1;
    else if (fsystem <  2500)                                   // 1.25MHz < fsystem <  2.5MHz
        UCSCTL1 = DCORSEL_2;
    else if (fsystem <  5000)                                   // 2.5MHz  < fsystem <    5MHz
        UCSCTL1 = DCORSEL_3;
    else if (fsystem <  10000)                                  // 5MHz    < fsystem <   10MHz
        UCSCTL1 = DCORSEL_4;
    else if (fsystem <  20000)                                  // 10MHz   < fsystem <   20MHz
        UCSCTL1 = DCORSEL_5;
    else if (fsystem <  40000)                                  // 20MHz   < fsystem <   40MHz
        UCSCTL1 = DCORSEL_6;
    else
        UCSCTL1 = DCORSEL_7;

    __bic_SR_register(SCG0);                                    // Re-enable FLL

    while (UCSCTL7 & DCOFFG) {                                  // Check DCO fault flag
        UCSCTL7 &= ~DCOFFG;                                     // Clear DCO fault flag

        // Clear the global fault flag. In case the DCO caused the global fault flag to get
        // set this will clear the global error condition. If any error condition persists,
        // global flag will get again.
        SFRIFG1 &= ~OFIFG;
    }

    __bis_SR_register(srRegisterState);                         // Restore previous SCG0

    if (mode == 1) {                                            // fsystem > 16000
        SELECT_MCLK_SMCLK(SELM__DCOCLK + SELS__DCOCLK);         // Select DCOCLK
    }
    else {
        SELECT_MCLK_SMCLK(SELM__DCOCLKDIV + SELS__DCOCLKDIV);   // Select DCODIVCLK
    }
}