Part Number:MSP430F5359
Folks:
In SLAU208Q (June 2008–Revised March 2018), the MSP430x5xx and MSP430x6xx Family User's Guide, Table 6-20 indicates that instruction opcodes in the regions 10C0 through 10FF and 11C0 through 11CF are all reserved. See below.
These two code spaces are where the SWPB.B and SXT.B instructions could live but these instructions are essentially meaningless.
Oddly enough, as long as you specify them using the "X" (MSP430 "Extended" architecture) style, the IAR icc430 C Compiler (in its latest released version) accepts those instruction mnemonics and generates the expected opcodes in those two regions:
I ASSUME that those instructions won't actually be decoded and correctly executed by the various MSP430X processors. Is that assumption correct? What will the processors actually do if handed this code?
And if my first assumption is correct, then I further ASSUME that this is a bug in the IAR compiler/assembler and I ought to report it to IAR?
Atlant