what is the operational difference between using Host-Bus-8 mode in peripheral mode vs. in sram mode?
I have an application using lm3s5r31 with the 8-bit bus and a 515KB async SRAM. The same interface has several "peripheral" 8-bit D-type flip flops attached to the bus and the /WR and /CS1 (EPIOS27) lines. The circuit uses ADMUX and the ALE (EPIOS30). The sram is attached to /CS0 (EPIOS26).
I have a few thoughts about this.
First thought. I can just treat all peripherals and SRAM as SRAM (not as peripheral), with the /CS pins selecting the appropriate device based on address.
Second thought. I read in the datasheet that one chip select can access "peripheral" devices, while the other chip select can access "SRAM" devices. But I don't know what the difference between these two modes. It seems like I would like to have peripheral access separate from sram access, but I don't know if this is necessary.
Also, the datasheet reads:
"In the EPIADDRMAP register...... If both the EPADR and the ERADR are not 0x0, then CS0n is asserted for the address range defined
by EPADR and CS1n is asserted for the address range defined by ERADR."
where the EPADR is related to the "peripheral" device range, and the ERADR is related to the SRAM range. My circuit, however, has the SRAM tied to CS0, so I wonder if this is a problem?
any help here is appreciated.