Part Number:DAC37J82
I am using a DAC37j82 in a system. A disturbance in the system -- most likely the DAC clock -- sometimes stops the DAC from outputting data. The problem is that I can't find a way to detect that the DAC has stopped, short of looking at its output.
I am using the DAC in coarse mixing mode at fs/2 with a DAC clock of 512MHz interpolated by 2 for a JESD sample rate of 256Msps. I use a single JESD lane and only provide the I component. I am configured for JESD class 0 operation.
I have looked at all registers, including alarm registers -- config100 through config109 -- (after writing to clear the alarms and then waiting) and they have the same values whether the DAC outputting or not. The SYNC signal from the DAC is high in either case as well.
I am using the DAC with a Xilinx JESD core and I have found that I can restore normal operation by asserting the JESD core reset bit (which auto-clears and restarts the Xilinx JESD core). But the problem, again, is that I can't detect the condition.
One alarm bit in particular (config100, bit1 = read_error) is concerning because it is always set whether the DAC is outputting or not. Also, bit0 in that register (read_empty) is never set. That seems contradictory since reading with FIFO empty should mean that the FIFO was empty. If the read_error bit behaved as I would expect, I could probably use it to tell me that there is a JESD link issue.
Thanks, Lance