CCS/F28M36P63C2: ADCRESULT2 does not update

Part Number:F28M36P63C2

Tool/software: Code Composer Studio

Hello all,

i am having an issue i with my ADC configuration. Please see attached images. There are three sinusoidal sync pulses of same amplitude but different phases being read by three ADC channels. Each of the channels have to read this sync pulse and an additional DC offset calibrated in my docking board. The ADC conversions of the three inputs are SOC2, SOC3 and SOC4. But when i look at the ADC results in the watch window(see image attached of watch window),  I can only see SOC3 and SOC 4 update its values. SOC2 remains frozen and only reads the DC offset much like other ADC results in the image. What could cause this to happen?? i can rule out hardware issues as i measured the offset on the respective pins and also measure the sync pulses to be identical in amplitude and physically checked if that voltage is being fed into all three pins.

The issue is only with SOC2 and the peculiar thing is when i change SOC2 to other adc channels, the problem persists, which leads me to believe it must be something to do with the ADC configuration.

my ADC config code is below. And i verified that  Adc1Regs.ADCSOCFRC1.all register is set to 0x007f and that there are no overwrites to this value.

void ConfAdc(void)
{

	// Configure ADC
	    EALLOW;

	    Adc1Regs.ADCCTL2.bit.ADCNONOVERLAP = 1;     // Enable non-overlap mode i.e.
	                                                // conversion and future
	                                                // sampling
	                                                // events dont overlap

	    Adc1Regs.ADCCTL1.bit.INTPULSEPOS   = 1;     // ADCINT1 trips after
	                                                // AdcResults latch

	    Adc1Regs.INTSEL1N2.bit.INT1E       = 1;     // enable ADCINT1

	    Adc1Regs.INTSEL1N2.bit.INT1CONT    = 0;     // Disable ADCINT1 Continuous
	                                                // mode

	    Adc1Regs.INTSEL1N2.bit.INT1SEL     = 6;     // Setup EOC6 to trigger ADCINT1
	                                                // to fire
	    Adc1Regs.ADCINTSOCSEL1.all = 0x0000; 	// No ADCInterrupt will trigger SOCx
	    Adc1Regs.ADCINTSOCSEL2.all = 0x0000;
//	    Adc1Regs.ADCSOC0CTL.bit.CHSEL      = 0x4;   // Set SOC0 channel select to
//	                                                // ADC1A4 for Vout
	    Adc1Regs.ADCSOC0CTL.bit.CHSEL      = 0x2;   // Set SOC0 channel select to
	                                                // ADC1A2 for Vout
	    Adc1Regs.ADCSOC1CTL.bit.CHSEL      = 0x7;   // Set SOC1 channel select to
	                                                // ADC1A7, for Iout
//	    Adc1Regs.ADCSOC1CTL.bit.CHSEL      = 0x3;   // Set SOC1 channel select to
//	                                                // ADC1A3, for Iout
	    Adc1Regs.ADCSOC2CTL.bit.CHSEL      = 0x8;   // Set SOC2 channel select to
	                                                // ADC1B0,for VinA
	    Adc1Regs.ADCSOC3CTL.bit.CHSEL      = 0xb;   // Set SOC3 channel select to
	                                                // ADC1B3,for VinB
	    Adc1Regs.ADCSOC4CTL.bit.CHSEL      = 0xf;   // Set SOC4 channel select to
	                                                // ADC1B7,for VinC
	    Adc1Regs.ADCSOC5CTL.bit.CHSEL      = 0x3;   // Set SOC5 channel select to
	                                                // ADC1A3,for VoltagePot
	    Adc1Regs.ADCSOC6CTL.bit.CHSEL      = 0x4;   // Set SOC6 channel select to
	                                                // ADC1A4,for CurrentPot

	    AnalogSysctrlRegs.TRIG1SEL.all     = 0;     // Assigning ADC Trigger 1 to Nothing
//	    AnalogSysctrlRegs.TRIG1SEL.all     = 5;     // Assigning EPWM1SOCA to
//	                                                // ADC TRIGGER 1 of the ADC module

	    Adc1Regs.ADCSOC0CTL.bit.ACQPS      = 6;     // Set SOC0 S/H Window to 7 ADC
	                                                // Clock Cycles, (6 ACQPS plus
	    Adc1Regs.ADCSOC1CTL.bit.ACQPS      = 6;     // Set SOC1 S/H Window to 7 ADC
	                                                // Clock Cycles, (6 ACQPS plus
	    Adc1Regs.ADCSOC2CTL.bit.ACQPS      = 6;     // Set SOC2 S/H Window to 7 ADC
	                                                // Clock Cycles, (6 ACQPS plus
	    Adc1Regs.ADCSOC3CTL.bit.ACQPS      = 6;     // Set SOC3 S/H Window to 7 ADC
	                                                // Clock Cycles, (6 ACQPS plus
	    Adc1Regs.ADCSOC4CTL.bit.ACQPS      = 6;     // Set SOC4 S/H Window to 7 ADC
	                                                // Clock Cycles, (6 ACQPS plus
	    Adc1Regs.ADCSOC5CTL.bit.ACQPS      = 6;     // Set SOC5 S/H Window to 7 ADC
	                                                // Clock Cycles, (6 ACQPS plus
	    Adc1Regs.ADCSOC6CTL.bit.ACQPS      = 6;     // Set SOC6 S/H Window to 7 ADC
	                                                // Clock Cycles, (6 ACQPS plus

//	    AdcRegs.ADCINTFLG.bit.ADCINT1 = 0;
	    AdcRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;// clear interrupt flag for ADCINT1
	    AdcRegs.ADCSOC0CTL.bit.TRIGSEL = 5;			//SOC0 from Analog Trigger 1
	    AdcRegs.ADCSOC1CTL.bit.TRIGSEL = 5;			//SOC1 from Analog Trigger 1
	    AdcRegs.ADCSOC2CTL.bit.TRIGSEL = 5;			//SOC2 from Analog Trigger 1
	    AdcRegs.ADCSOC3CTL.bit.TRIGSEL = 5;			//SOC3 from Analog Trigger 1
	    AdcRegs.ADCSOC4CTL.bit.TRIGSEL = 5;			//SOC4 from Analog Trigger 1
	    AdcRegs.ADCSOC5CTL.bit.TRIGSEL = 5;			//SOC5 from Analog Trigger 1
	    AdcRegs.ADCSOC6CTL.bit.TRIGSEL = 5;			//SOC6 from Analog Trigger 1

		Adc1Regs.ADCSOCFRC1.bit.SOC0 = 1; 				// kick-start ADC
		Adc1Regs.ADCSOCFRC1.bit.SOC1 = 1; 				// kick-start ADC
		Adc1Regs.ADCSOCFRC1.bit.SOC2 = 1; 				// kick-start ADC
		Adc1Regs.ADCSOCFRC1.bit.SOC3 = 1; 				// kick-start ADC
		Adc1Regs.ADCSOCFRC1.bit.SOC4 = 1; 				// kick-start ADC
		Adc1Regs.ADCSOCFRC1.bit.SOC5 = 1; 				// kick-start ADC
		Adc1Regs.ADCSOCFRC1.bit.SOC6 = 1; 				// kick-start ADC

	    EDIS;
}

Any suggestion is greatly appreciated,

Thank you,

Srini