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RTOS/AM6548: MSI Interrupt Generation in EP Mode

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Part Number:AM6548

Tool/software: TI-RTOS

Hello,

I am trying to configure an EP (FPGA) to be able to trigger MSI interrupts on the AM6546 processor (RC). Unfortunately, I am not sure which address should the EP write TLP target.

In the SPRUHY8H for 66AK2G1x processor (Multicore DSP+Arm ® KeyStone II System-on-Chip (SoC)) for example, stands following:

The memory write transactions to generate MSI interrupts in RC are actually targeted at PCIE_MSI_IRQ
register. The MSI interrupt is generated as a result of the one of 32 events that is triggered by a write of
MSI vector value to PCIE_MSI_IRQ register in RC.

The address of the PCIE_MSI_IRQis available as well (2180 0054h). However, in the SPRUID7B for AM65x/DRA80xM Processors (my RC) there is no mention of such register.

I would appreciate any help.

Best regards,

Dušan


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