Data Bus Pin Swapping on SDRAM for AM3505

Hello,

I am in the process of bringing-up/debugging a new design which contains a AM3505.  I'm experiencing a number of difficulties programming either the NAND Flash or the SDRAM using the Flash tool (v1.6).  To that end, I am examining each block of my design in-turn.

For the SDRAM (a 2Gbit Micron MT47H128M16RT), we pin swapped the data bus between the processor and the SRAM to aid routing - we only swapped within byte lanes as follows:

SDRAM              Processor

• D0                       D5
• D1                       D6
• D2                       D4
• D3                       D1
• D4                       D2
• D5                       D0
• D6                       D3
• D7                       D7

• D8                       D15
• D9                       D12
• D10                     D13
• D11                     D8
• D12                     D11
• D13                     D10
• D14                     D9
• D15                     D14

I can't think of any reason why this would cause a problem, but as I'm having difficulties I'm just covering all my bases.

Can someone confirm that swapping these pins is acceptable - or not?

Thank you,

Kevin Taberski