TLV320ADC3101: Register Settings for 48 kHz sampling I2S 32-Fs Format

Part Number:TLV320ADC3101

My project uses a TLV320ADC3101 driving into a TAS5755M Amplifier.

I've had some advice on this from TI and have been advised to change the MCLK input to the ADC3101 from 12 MHz to 3.072 MHz.  What I need are the register settings to generate stereo, 16 bits per left/and 16 bits per right I2S 32-Fs format (see picture from TAS5755M datasheet), 

I'm looking for the setting to use a 3.072 MHz input clock to MCLK to generate the second line under fs = 48 kHz in Table 1 of the TLV320ADC3101 datahsheet see picture

It's not clear to me whether or not I should run the PLL or not or what value I should end up with for ADC_FS or AOSR.

Thanks

Ted