AM6548: UDMA uart rx write latency

Part Number:AM6548

I am trying to setup the uart0 rx udma so that it will write the data to ddr on every byte received vs every ~64bytes(guessing udma fifo gets filled). It looks like the udma has the data in some fifo since PDMA_PSILCFG_REG_DEBUG_1.Z is incrementing every byte I send. I don’t see a way to make it write that data to ddr when it only has 1 byte though. How would I set it up to do smaller writes?