TMS320F28335: TMS320f28335

Part Number:TMS320F28335

Hello

I am having problems with the SoC  from EPwm1A and B. I am triggering a SoC on CTR= 0 for SOCA and CTR=TPCTR for SOCB. The results are periodic bad readings on both ADCINA3/B3 at the same instance in time. When I only enable SoC on CTR=0 SOCA (or CTR=TPCTR SOCB), i.e. half the frequency, all results are ok. I have also tried trigging off of EPwm2 SOCA CTR=TPCTR (instead of EPwm1B) still get bad results. 

I have adjusted the timing, slowed down the ISR loop, but get the same results.

Any help/suggestions would be appreciated 

Thank

John

I have broken my code in 4 sections

1) EPWM Config

2) ADC Config

3) Main

4) Interrupts

My EPWMs are setup as follows:

// EPWM Module 1 config
    EPwm1Regs.TBPRD = PWM1_TIMER_TBPRD; //
    EPwm1Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero
    EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Symmetrical mode
    EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Master module
    EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
    EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Sync down-stream module
    EPwm1Regs.TBCTL.bit.CLKDIV = 0x0000; // /1 TBCLK=SYSCLKOUT/(HSPCLKDIV*CLKDIV)
    EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0x0000; //1 TBCLK=SYSCLKOUT/(HSPCLKDIV*CLKDIV)
    EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
    EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero

    EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // set actions for EPWM1A
    EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;

    EPwm1Regs.DBCTL.bit.IN_MODE = 0x00; // EPWM1A Source, thus do not need AQCTLB Configured
    EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
    EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
    EPwm1Regs.DBFED = 50; // FED = 50 TBCLKs
    EPwm1Regs.DBRED = 50; // RED = 50 TBCLKs

    EALLOW;
   // EPwm1Regs.TZCTL.bit.TZA = 1; // Forced high
   // EPwm1Regs.TZCTL.bit.TZB = 1; // Forcec high
   // EPwm1Regs.TZEINT.bit.CBC = 0; // No Interrupt for One-Shot
   // EPwm1Regs.TZEINT.bit.OST = 0; // No Interrupt for Cycle to Cycle
  // EPwm1Regs.TZSEL.all = 0; // No HW trip signal
    EDIS;

      EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOCA (Bit11)
     EPwm1Regs.ETSEL.bit.SOCASEL = 0x1; // SOC A Pulse generate when TPCTR = 0;
     EPwm1Regs.ETPS.bit.SOCAPRD = 1;        // Generate pulse on 1st event
      EPwm1Regs.ETSEL.bit.SOCBEN = 1; // Enable SOCB (Bit11)
      EPwm1Regs.ETSEL.bit.SOCBSEL = 0x2; // SOC B Pulse generate when TPCTR = 0;
      EPwm1Regs.ETPS.bit.SOCBPRD = 1;        // Generate pulse on 1st event

      EPwm1Regs.ETSEL.bit.INTSEL = 1; //ET_CTR_ZERO;
      EPwm1Regs.ETSEL.bit.INTEN = PWM1_INT_ENABLE;  // Enable INT
      EPwm1Regs.ETPS.bit.INTPRD = ET_1ST;           // Generate INT on 1st event

 // EPWM Module 2 config
    EPwm2Regs.TBPRD = PWM1_TIMER_TBPRD; // Period
    EPwm2Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero
    EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Symmetrical mode
    EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Slave module
    EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
    EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through
       EPwm2Regs.TBCTL.bit.CLKDIV = 0x0000; // /1 TBCLK=SYSCLKOUT/(HSPCLKDIV*CLKDIV)
       EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0x0000; //1 TBCLK=SYSCLKOUT/(HSPCLKDIV*CLKDIV)
    EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
    EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero
    EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // set actions for EPWM2A
    EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR;
    EPwm2Regs.DBCTL.bit.IN_MODE = 0x00; // EPWM2A Source
    EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
    EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
    EPwm2Regs.DBFED = 50; // FED = 50 TBCLKs
    EPwm2Regs.DBRED = 50; // RED = 50 TBCLKs

    EALLOW;
    EPwm2Regs.TZCTL.bit.TZA = 1; // Forced high
    EPwm2Regs.TZCTL.bit.TZB = 1; // Forcec high
    EPwm2Regs.TZEINT.bit.CBC = 0; // No Interrupt for One-Shot
    EPwm2Regs.TZEINT.bit.OST = 0; // No Interrupt for Cycle to Cycle
    EPwm2Regs.TZSEL.all = 0; // No HW trip signal
    EDIS;

   // EPwm2Regs.ETSEL.bit.SOCAEN = 1; // Enable SOCA (Bit11)
   // EPwm2Regs.ETSEL.bit.SOCASEL = 0x2; // SOC A Pulse generate when TPCTR = TPRD;
    // EPwm2Regs.ETPS.bit.SOCAPRD = 1;        // Generate pulse on 1st event

My ADC is configured as followed:

// Configure ADC
  EALLOW;
  SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1;
 // ADC_cal();
  EDIS;

  //ADCTRL3
    AdcRegs.ADCREFSEL.bit.REF_SEL = 0x0; // Voltage Reference ? assuming internal
    AdcRegs.ADCTRL3.bit.ADCBGRFDN = 0x3; // Power up bandgap/reference/ADC circuits
    AdcRegs.ADCTRL3.bit.ADCPWDN = 0x1; // Power up bandgap/reference/ADC circuits
    AdcRegs.ADCTRL3.bit.ADCCLKPS = 0x0; //HSPCLK passed thru
    AdcRegs.ADCTRL3.bit.SMODE_SEL = 0x1; // 1)Simultaneous sampling mode 0)Sequential

   DELAY_US(ADC_usDELAY);         // Delay before converting ADC channels

   //ADCTRL1
    AdcRegs.ADCTRL1.bit.SUSMOD = 0x0;
       AdcRegs.ADCTRL1.bit.ACQ_PS = 0x8; //Acq window size: ("6"+1)xADClk period 7*1/(75e6/2)=183ns
    AdcRegs.ADCTRL1.bit.CPS = 0x1; //  0=>ADCLK=HSPCLK/2  (1=>ADCLK=HSPCLK/2)
       AdcRegs.ADCTRL1.bit.CONT_RUN = 0x0;
      AdcRegs.ADCTRL1.bit.SEQ_OVRD = 0x0;
      AdcRegs.ADCTRL1.bit.SEQ_CASC = 0x1;    //
   //ADCTRL1
       AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 0x1;// Enable SOCA from ePWM to start SEQ1
       AdcRegs.ADCTRL2.bit.EPWM_SOCB_SEQ= 0x1;// Enable SOCA from ePWM to start SEQ1
       AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 0x1;  // Enable SEQ1 interrupt (every EOS)

   //==
    AdcRegs.ADCMAXCONV.all = 0x0006;        //4 double conv's sequencer
    AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0;  //0,1 Setup ADCINA0/B0 
    AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x0;  //2,3 Setup ADCINA0/B0 
    AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x1;  //4,5 Setup ADCINA1/B1
    AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x2;  //6,7  Setup ADCINA2/B2
   AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x3;  //8,9 Setup ADCINA3/B3 
   AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x0;  //10,11 Setup ADCINA0/B0 
   AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x3;  //12,13 Setup ADCINA3/B

 My Main

#pragma CODE_SECTION(epwm1_timer_isr, "ramfuncs");
#pragma CODE_SECTION(adc_isr, "ramfuncs");
#pragma CODE_SECTION(CpuTimer1_int13_isr, "ramfuncs");
#pragma CODE_SECTION(FOC_Update, "ramfuncs");
#pragma CODE_SECTION(ADC_ResultSave, "ramfuncs");
#pragma CODE_SECTION(ADC_ResultUpdate, "ramfuncs");
#pragma CODE_SECTION(commo_routine, "ramfuncs");

main(void)
{
  InitSysCtrl();
  DisableDog();

   DINT;// Disable CPU interrupts
   InitPieCtrl();
   IER = 0x0000;
   IFR = 0x0000;
      InitPieVectTable();

  EALLOW;  // This is needed to write to EALLOW protected registers
      PieVectTable.EPWM1_INT = &epwm1_timer_isr;
      PieVectTable.ADCINT = &adc_isr;
         PieVectTable.XINT13 = &CpuTimer1_int13_isr;  // CPU1 32bit Timer INT13
     EDIS;

     EALLOW;
     XIntruptRegs.XNMICTR = 0; //Counter (CPU_Timer1 = INT13)
     EDIS;

     MemCopy(&RamfuncsLoadStart, &RamfuncsLoadEnd, &RamfuncsRunStart);
  InitFlash();

  EPwm1TimerIntCount = 0;
  MainLoopCount = 0;

     IER |=  M_INT1 | M_INT3 | M_INT13; //CPU Interrupt 13 (CPUTimer1) and 3(ePWM1): Need to set IFR and IER
     PieCtrlRegs.PIEIER3.bit.INTx1 = 1;  // ePWM1_INT_ENABLE (ePWM1)
     PieCtrlRegs.PIEIER1.bit.INTx6 = 1;

   EINT;   // Enable Global interrupt INTM
   ERTM;   // Enable Global realtime interrupt DBGM

//========= Application  intialization =================
  

//====================================================

 //=== Put the Flash to sleep ========
 // EALLOW;
 // FlashRegs.FPWR.bit.PWR = FLASH_SLEEP;
 //=================================
 // FlashRegs.FPWR.bit.PWR = FLASH_SLEEP;
 // EDIS;

//=============== State Machine  ====================
State = 1;
while(1)
 {
    
 if(commo_flag)
   { commo_flag = 0;
       commo_routine();

     }
 if(adc_flag)
   {
  adc_flag = 0;
  ADC_ResultUpdate();
  //ADC_VdcMotorTmpUpdate();
  //CurrentPeakUpdate();

   }

 if(foc_flag)
   {
   foc_flag = 0;
   FOC_Update();

   }

  switch(State)
   {
  case 1:
   Initial_Configure();
  break;
  case 2:
   Initial_Loop();
  break;
  case 3:
      Run_Configure();
  break;
  case 4:
      Run_Loop();
  break;
  case 5:
   Fault_Loop();
  break;
        case 6:
            EEPROMB_Loop();
        break;
   }
  MainLoopCount++;
 }
}

MY Interupts

interrupt void CpuTimer1_int13_isr(void)  // CPU1 32bit Timer INT13
{
  commo_flag = 1; //change 10aug2018

  CpuTimer1Regs.TCR.bit.TIF = 1; //change 10aug2018
  PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; //change 10aug2018
}

interrupt void adc_isr(void)
{

   // EPwm1Regs.ETSEL.bit.SOCAEN = 0; // Disable SOCA (Bit11)
   // EPwm1Regs.ETSEL.bit.SOCBEN = 0; // Disable SOCA (Bit11)
 ADCCount++; //For Testing
 ADC_ResultSave();
 adc_flag = 1;

    EPwm1Regs.ETCLR.bit.SOCA = 1;// Clears ETFLG[SOCA] Flag
    EPwm1Regs.ETCLR.bit.SOCB = 1;// Clears ETFLG[SOCA] Flag
    EPwm1Regs.ETCLR.bit.INT= 1;// Clears ETFLG[SOCA] Flag
   // EPwm2Regs.ETCLR.bit.SOCA = 1;// Clears ETFLG[SOCA] Flag
   // EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOCA (Bit11)
    // EPwm2Regs.ETSEL.bit.SOCAEN = 1; // Enable SOCA (Bit11)

 AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1;         // Reset SEQ1
 //AdcRegs.ADCTRL2.bit. = 1;         // Reset SEQ1

 AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1;       // Clear INT SEQ1 bit
 //AdcRegs.ADCST.bit.INT_SEQ2_CLR = 1;
 PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}

interrupt void epwm1_timer_isr(void)
{
 EPwm1TimerIntCount++;
 FOC_Update();
 foc_flag = 1;

    EPwm1Regs.ETCLR.bit.INT = 1;
 PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}