SN74AVC4T774: Questions

Part Number:SN74AVC4T774

Team,

1)      If I power the B side of the level translator and the A Side is unpowered and I have a pull up to VCCA on the OE_N line and the direction lines are tied to either GND or VCC A.

1. When the A Side power rail is ramped up will direction or data lines glitch? (Considering B Side is powered and A Side is ramping up)
2. While the OE_N is high do both sides of the part need to have pull downs to provide a low or high on the IO lines? (Including the IOs which will be outputs)
3. Is there any higher current on ICCA or ICCB in these states?

2)      If I power the A Side of the level translator and the B Side is unpowered and I have a pull up to VCCA on the OE_N line and the direction lines are tied to either GND or VCC A.

1. When the B Side power rail is ramped up will there be any data line or direction glitches?
2. While the OE_N is high does the lines which would be normally outputs required biasing resistors?
3. Is there an higher current on ICCA or ICCB in these states?