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OMAP-L137: DMA block transfer - data not arriving in destination

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Part Number:OMAP-L137

I have an application which currently uses sample by sample interrupts to read in data from the McASP and I am trying to move it to a DMA based solution. 

Since I am not familiar with the DMA on TI devices, I set up a little test to transfer a very small block of data with manually triggered DMA , to help me confirm that I am programming up the DMA correctly, before trying to interface it to peripherals. 

Everything seems to be working exactly as I would expect - with one major exception - I am unable to see the data arrive at the expected destination. 

My setup in the param block

<LF>
DSP: INFO: DMA_PARAM2_SRC @ 0x01c04044 = 0xc3e5d170<LF>
<LF>
DSP: INFO: DMA_PARAM2_A_B_CNT @ 0x01c04048 = 0x00040004<LF>
<LF>
DSP: INFO: DMA_PARAM2_DST = 0xc3e5d188<LF>
<LF>
DSP: INFO: DMA_PARAM2_SRC_DST_BIDX = 0x00040004<LF>
<LF>
DSP: INFO: DMA_PARAM2_LINK_BCNTRLD = 0x0000ffff<LF>
<LF>
DSP: INFO: DMA_PARAM2_SRC_DST_CIDX = 0x00000000<LF>
<LF>
DSP: INFO: DMA_PARAM2_CCNT = 0x00000001<LF>

 

I (repeatedly) set the appropriate bit in the ESR to manually trigger the transfer and then I monitor the IPR. 

I can see the bit in the IPR being set at the end of each intermediate (and the final)  transfer.

I can see the SRC and DST registers update with the new addresses on each intermediate transfer.

I can see the TCSTAT register in the TC updating the pointer to the FIFO and there are no errors in the TC's ERRSTAT

DMA_TC1_TCSTAT = 0x00000100 and  DMA_TC1_ERRSTAT = 0x00000000

then after the next intermediate transfer

DMA_TC1_TCSTAT = 0x00000900 and  DMA_TC1_ERRSTAT = 0x00000000

(This example shows TC 1, but I have also tried changing DMAQNUM and sending the requests to TC0) 

Basically,everything seems to be operating exactly as I would expect it to. However, when I look at my destination address (both reading it in the code and looking at the memory location with the debugger) the data has not been moved to the new location.

I feel like I've tracked the DMA transfer through the various stages but I am obviously missing something..............

What could be going on? Where to look next? 

Thanks in advance

Lorraine 


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