Hi,
Since I am not sure to understand everything correctly from the datasheet, is it possible that you confirm (or not) the following points :
1)
For a new design with the Shannon DSP, we are considering to use an input "Core_clk" of 125 MHz so that the internal cores can run (operational conditions) at "Core_clk" * 8 = 1GHz.
THe DSP will boot either from EMIF, or SRIO.
BOOT_MODE(12..10) will be set to "111" which will cause the dsp to operate at 813.8 MHz during boot.
Is this correct ?
2)
We also plan to use the internal Netcp accelerator, and in order to simplify our clock tree, we are going to NOT USE PA_SS clock input and
run the NetCP engine from CORE_clk instead (PACLKSEL=0).
According to fig 7-25 of the TMS320c6678 datasheet(feb-2012), this seems to be a reasonnable solution since the PA_SS PLL reference input path does provide a clock selector.
Is this correct ? or are there some particular issues or problems that could occur from that approach ?
What is the advantage of having an independent clock input for the NEtCP engine ?
Thank you for you support,
with best regards,
Bruno