Hello All,
I am using CC430F6137 with IAR EW 5.20
My problem is after some time (we tested with 1 hour and more (about 3 days))
there is a shift in time shown on the LCD (read from RTC registers) (5 min in an hour & 1 hour in 3 days!!)
my MCU works with an external 32.768KHz Xtall (MS1V-T1K) with 12pF Internal capacitor.
i have checked the ACLK clock on an external pin the clock is as below:
as you see above the frequency of ACLK clock is 32.89 KHz not 32768 Hz
Here is my code:
// Enable External 32kHz XTALL
P5SEL |= 0x03; // Select XIN, XOUT on P5.0 and P5.1
UCSCTL6 &= ~(XT1OFF); // XT1 On, Increased drive strength for XT1 LF mode.
// XT1 oscillator operating range in HF mode is 8MHz to 16MHz.
UCSCTL6 |= XCAP_3; // Internal load cap
UCSCTL3 |= SELA__XT1CLK; // Select XT1 as FLL reference
UCSCTL4 = SELA__XT1CLK | SELS__DCOCLKDIV | SELM__DCOCLKDIV;
// Configure CPU clock for 12MHz
_BIS_SR(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_5; // Select suitable range
UCSCTL2 = FLLD_1 + 0x16E; // Set DCO Multiplier
_BIC_SR(SCG0); // Enable the FLL control loop
// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 12 MHz / 32,768 Hz = 375000 = MCLK cycles for DCO to settle
__delay_cycles(375000);
// Loop until XT1 & DCO stabilizes, use do-while to insure that
// body is executed at least once
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
SFRIFG1 &= ~OFIFG; // Clear fault flags
}
while ((SFRIFG1 & OFIFG));
also i have added a 12 pF external capacitor and disabled the internal cap but no use.
can any one help me ?
thank you in advance