Part Number:TMS570LC4357
Tool/software: TI C/C++ Compiler
I am using the TI ARM compiler (tried version 5.1.6 and 16.9.4) to compile code for the TMS570LC43xx device, which is an R5 cache based device. When I invoke opt_for_speed=2 or greater, the compiler forces the .text section of each file to a 16 byte alignment. That creates lots of wasted flash space with holes of 2 to 14 bytes. I assume this is because the compiler is aligning the .text section to a cache page. It seems a pretty high code size hit for the speed optimization. Is there a way to turn off the forced alignment and still get the other speed enhancements that come with opt_for_speed=2?