TMS320F28379D: ADCCLK Period

Hello,

My name is Troy and my partner and I are using the TMS320F28379D launchpad for prototyping a senior design project, specifically the on board ADC.

We are interested in running the ADC in 16 bit differential mode as fast as possible. The ADCCLK is tied to SYSCLK through a divide, and has a divide by 1 option listed (meaning we originally thought that the ADC clk could run at 200MHz).

However, I saw in sprs880j.pdf on page 103 that the minimum sample and hold time = 320ns, and that 1 ADCCLK cycle must = Tsh = 320ns 

Is this spec accurate? If so is there any way to run the ADC faster than 3.125MHz and still get correct operation?

Thank you in advanced for the clarification.