Hi,
Recently we have tested the LMK01801 Non-PLL buffer, the following observation was found:
Clk out group:CG-2(CLK OUT:4) was programed to out the LVCMOS, but it provides 2.85V DC output instead of clock, this problem exist for all type of inputs & different frequency. At the same time CLK OUT:0 to 3 is working properly(LVDS mode is used). What will be the reason behind this ?
Pin settings of LMK01801 for your reference:
CLK in: 10MHz from OCXO
PIN control: LOW
CLKoutTYPE_0: LOW
CLKoutTYPE_1: Floating(the voltage measured at this pin is 1.55V)
CLKoutTYPE_2: floating
CLKoutDIV_0: low
CLKoutDIV_1: low
CLKoutDIV_2: float
regards,
Rajesh