ADS42JB49EVM: SYNC~ not asserted

Part Number:ADS42JB49EVM

Hi,

I have interfaced ADS42JB49EVM, TSW14J10 and KC705. ADC sampling clock is 156.25MHz, line rate of 3.125Gbps and LMF_221.

At any time I am going to drive only channel A inputs. 20x mode states that one lane per ADC will be active. So, even if only one channel is active are both ADC functional ? How do I disable the unused lanes in 20x mode and know which of them are active (DA0/DA1 and DB0/DB1 to connect to FPGA side rx pins).

Though sysref is captured on FPGA side I do not get link synchronized. I have inserted the configuration file. (Please visit the site to view this file)How do I proceed in debugging.

Thanks,

Yogitha